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CoX Peripheral Interface V2.1
API Reference
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CoX Peripheral Interface V2.1
API Reference
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Values that show SysCtl Peripheral Source Clock The following are values that can be passed to the xSysCtlPeripheralClockSourceSet() API as the ulPeripheralsrc parameter. More...
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Defines | |
| #define | xSYSCTL_WDT0_EXTSL |
| Watch dog clock source is external xxkHz crystal clock. | |
| #define | xSYSCTL_WDT0_HCLK_2048 |
| Watch dog clock source is HCLK/x clock. | |
| #define | xSYSCTL_WDT0_INTSL |
| Watch dog clock source is internal 10 kHz oscillator clock. | |
| #define | xSYSCTL_ADC0_MAIN |
| ADC clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_ADC0_PLL |
| ADC clock source is PLL clock. | |
| #define | xSYSCTL_ADC0_INT |
| ADC clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_TIMER0_MAIN |
| Timer0 clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_TIMER0_EXTSL |
| Timer0 clock source is external 32 KHz crystal clock. | |
| #define | xSYSCTL_TIMER0_HCLK |
| Timer0 clock source is HCLK. | |
| #define | xSYSCTL_TIMER0_EXTTRG |
| Timer0 clock source is external trigger. | |
| #define | xSYSCTL_TIMER0_INT |
| Timer0 clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_TIMER1_MAIN |
| Timer1 clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_TIMER1_EXTSL |
| Timer1 clock source is external 32kHz crystal clock. | |
| #define | xSYSCTL_TIMER1_HCLK |
| Timer1 clock source is HCLK. | |
| #define | xSYSCTL_TIMER1_EXTTRG |
| Timer1 clock source is external trigger. | |
| #define | xSYSCTL_TIMER1_INT |
| Timer1 clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_TIMER2_MAIN |
| Timer2 clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_TIMER2_EXTSL |
| Timer2 clock source is external 32kHz crystal clock. | |
| #define | xSYSCTL_TIMER2_HCLK |
| Timer2 clock source is HCLK. | |
| #define | xSYSCTL_TIMER2_EXTTRG |
| Timer2 clock source is external trigger. | |
| #define | xSYSCTL_TIMER2_INT |
| Timer2 clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_TIMER3_MAIN |
| Timer3 clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_TIMER3_EXTSL |
| Timer3 clock source is external 32 KHz crystal clock. | |
| #define | xSYSCTL_TIMER3_HCLK |
| Timer3 clock source is HCLK. | |
| #define | xSYSCTL_TIMER3_EXTTRG |
| Timer3 clock source is external trigger. | |
| #define | xSYSCTL_TIMER3_INT |
| Timer3 clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_UART0_MAIN |
| UART clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_UART0_PLL |
| UART clock source is PLL clock. | |
| #define | xSYSCTL_UART0_INT |
| UART clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_UART1_MAIN |
| UART clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_UART1_PLL |
| UART clock source is PLL clock. | |
| #define | xSYSCTL_UART1_INT |
| UART clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_UART2_MAIN |
| UART clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_UART2_PLL |
| UART clock source is PLL clock. | |
| #define | xSYSCTL_UART2_INT |
| UART clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_CAN0_MAIN |
| CAN clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_CAN0_PLL |
| CAN clock source is PLL clock. | |
| #define | xSYSCTL_CAN0_INT |
| CAN clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_PWMA_MAIN |
| PWMA clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_PWMA_EXTSL |
| PWMA clock source is external 32kHz crystal clock. | |
| #define | xSYSCTL_PWMA_HCLK |
| PWMA clock source is HCLK. | |
| #define | xSYSCTL_PWMA_INT |
| PWM0 and PWM1 clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_I2S0_MAIN |
| I2S clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_I2S0_PLL |
| I2S clock source is PLL. | |
| #define | xSYSCTL_I2S0_HCLK |
| I2S clock source is HCLK. | |
| #define | xSYSCTL_I2S0_INT |
| I2S clock source is internal 22 MHz oscillator clock. | |
| #define | xSYSCTL_FRQDIV_MAIN |
| frequency divide source is external 12 MHz crystal clock | |
| #define | xSYSCTL_FRQDIV_EXTSL |
| frequency divide source is external 32kHz crystal clock | |
| #define | xSYSCTL_FRQDIV_HCLK |
| frequency divide source is HCLK | |
| #define | xSYSCTL_FRQDIV_INT |
| frequency divide source is internal 22 MHz oscillator clock | |
| #define | xSYSCTL_PWMB_MAIN |
| PWMB clock source is external 12 MHz crystal clock. | |
| #define | xSYSCTL_PWMB_EXTSL |
| PWMB clock source is external 32 KHz crystal clock. | |
| #define | xSYSCTL_PWMB_HCLK |
| PWMB clock source is HCLK. | |
| #define | xSYSCTL_PWMB_INT |
| PWMB clock source is internal 22 MHz oscillator clock. | |
Values that show SysCtl Peripheral Source Clock The following are values that can be passed to the xSysCtlPeripheralClockSourceSet() API as the ulPeripheralsrc parameter.
The macros of General Peripheral Source Clock always like: ModuleName + n + SourceClock, such as xSYSCTL_WDT_EXTSL, xSYSCTL_ADC0_MAIN.
//! +-------------------------- +----------------+--------------------------+ //! |Peripheral Source Clock Set| CoX | NUC1xx | //! |---------------------------|----------------|--------------------------| //! |Those are all Non-Mandatory| Non-Mandatory | Y | //! | parameter,the Mandatory | | | //! | is variable naming | | | //! |ModuleName+n+SourceClock | | | //! |---------------------------|----------------|--------------------------| //! |xSYSCTL_WDT_EXTSL | Non-Mandatory | Y | //! |-------------------------- |----------------|--------------------------| //! |xSYSCTL_WDT_HCLK_2048 | Non-Mandatory | Y | //! |-------------------------- |----------------|--------------------------| //! |xSYSCTL_WDT_INTSL | Non-Mandatory | Y | //! |-------------------------- |----------------|--------------------------| //! |xSYSCTL_ADC0_MAIN | Non-Mandatory | Y | //! |-------------------------- |----------------|--------------------------| //! |xSYSCTL_ADC0_PLL | Non-Mandatory | Y | //! |-------------------------- |----------------|--------------------------| //! |...... | Non-Mandatory | Y | //! |-------------------------- |----------------|--------------------------| //! |xSYSCTL_PWMB_INT | Non-Mandatory | Y | //! |-------------------------- |----------------|--------------------------| //!
| #define xSYSCTL_WDT0_EXTSL |
| #define xSYSCTL_WDT0_HCLK_2048 |
| #define xSYSCTL_WDT0_INTSL |
| #define xSYSCTL_ADC0_MAIN |
| #define xSYSCTL_ADC0_INT |
| #define xSYSCTL_TIMER0_MAIN |
| #define xSYSCTL_TIMER0_EXTSL |
| #define xSYSCTL_TIMER0_EXTTRG |
| #define xSYSCTL_TIMER0_INT |
| #define xSYSCTL_TIMER1_MAIN |
| #define xSYSCTL_TIMER1_EXTSL |
| #define xSYSCTL_TIMER1_EXTTRG |
| #define xSYSCTL_TIMER1_INT |
| #define xSYSCTL_TIMER2_MAIN |
| #define xSYSCTL_TIMER2_EXTSL |
| #define xSYSCTL_TIMER2_EXTTRG |
| #define xSYSCTL_TIMER2_INT |
| #define xSYSCTL_TIMER3_MAIN |
| #define xSYSCTL_TIMER3_EXTSL |
| #define xSYSCTL_TIMER3_EXTTRG |
| #define xSYSCTL_TIMER3_INT |
| #define xSYSCTL_UART0_MAIN |
| #define xSYSCTL_UART0_INT |
| #define xSYSCTL_UART1_MAIN |
| #define xSYSCTL_UART1_INT |
| #define xSYSCTL_UART2_MAIN |
| #define xSYSCTL_UART2_INT |
| #define xSYSCTL_CAN0_MAIN |
| #define xSYSCTL_CAN0_INT |
| #define xSYSCTL_PWMA_MAIN |
| #define xSYSCTL_PWMA_EXTSL |
| #define xSYSCTL_PWMA_INT |
| #define xSYSCTL_I2S0_MAIN |
| #define xSYSCTL_I2S0_INT |
| #define xSYSCTL_FRQDIV_MAIN |
| #define xSYSCTL_FRQDIV_EXTSL |
| #define xSYSCTL_FRQDIV_HCLK |
| #define xSYSCTL_FRQDIV_INT |
| #define xSYSCTL_PWMB_MAIN |
| #define xSYSCTL_PWMB_EXTSL |